1. Field of the Invention
The present invention relates to a method for manufacturing bipolar transistors compatible with a CMOS integrated circuit manufacturing process.
The present invention more specifically relates to high speed bipolar transistors which find applications in fields such as high bit rate optical communications, radio-frequency connections in the very-high frequency range, automobile anti-collision radars, etc. and associated devices.
2. Discussion of the Related Art
A detailed example of the forming of bipolar transistors in which, conventionally, a spacer is formed between the base forming and emitter forming steps, will be described in relation with FIGS. 1A to 1I.
The collector forming and collector contacting steps, which will be performed in any conventional fashion known by those skilled in the art, will not be described in detail.
In this method, as shown in FIG. 1A, it is started from a semiconductor substrate 1, generally made of silicon, on which are successively formed a layer of a first insulator 2, a polysilicon layer 3, and a layer of a second insulator 4. The substrate is a solid substrate or a thin semiconductor layer resting on a support, for example, a semiconductor of opposite type or an insulator.
As shown in FIG. 1B, a window is then opened in second insulator layer 4 and polysilicon layer 3 at the location where a bipolar transistor is desired to be formed. A second layer 5 of the second insulator is deposited on the structure.
At the step illustrated in FIG. 1C, the second insulator is etched to form spacers around the window edges. Thus, the second insulator completely surrounds polysilicon layer 3 with an upper layer 7 and a lateral layer 8.
At the step illustrated in FIG. 1D, first insulator layer 2 is etched, using layers 7, 8 as a mask, by overetching, so that the opening penetrates under spacer 8 and under an internal peripheral portion of polysilicon layer 3.
After this, as illustrated in FIG. 1E, a selective semiconductor material epitaxy is performed on silicon substrate 1. A base layer 10, exposed in the opening formed between spacers 8 and in contact by its periphery with polysilicon 3 which forms a base contact layer, thus forms.
At the steps illustrated in FIGS. 1F and 1G, second spacers are formed inside of the window by successively depositing a layer of a first insulator 12 and a layer of a second insulator 13, in the way illustrated in FIG. 1F, then by anisotropically etching second insulator 13 to obtain spacers 15 of the second insulator, as illustrated in FIG. 1G.
As illustrated in FIG. 1H, after the step illustrated in FIG. 1G, first insulator layer 12 is isotropically etched to obtain the configuration of spacers 15, 16. After this, a layer of a doped semiconductor 18 of a biasing type opposite to that of base 10 and forming an emitter region in portion 19 of contact with the base region is deposited.
Finally, in the steps illustrated in FIG. 1I, an etching is performed, as shown, to delimit the emitter region, and a siliconizing is performed to obtain silicide layers 21 on the base contact area and 22 on the emitter area.
The steps of forming of second spacer 15, 16 illustrated in relation with FIGS. 1F to 1H are generally used since the emitter area must be separated from the base contacting area to avoid any emitter-base short-circuit. However, the forming of such spacers adds manufacturing steps to a conventional CMOS component manufacturing process. Further, the applicant has noted that this step sequence, that is, the forming of spacers between the base forming and the emitter forming, results in a disadvantage which had perhaps not been sufficiently noted previously. Indeed, after the spacer forming steps, a thin native oxide layer inevitably forms on the surface of base layer 10 and cleaning processes must be carried out to form the emitter. The elimination of this oxide layer must be performed immediately before the step of forming semiconductor layer 18. Such steps are difficult to implement within the same frame and the applicant has established that, as a necessary result, there remains a little amount of native oxide, which adversely affects the transistor properties and the quality of the emitter-base junction. As a result, the obtained transistors do not have such high performances as would be desired.
European patent application No 1117133 discloses a method wherein the upper portion of the intrinsic base layer is above the lower level of a spacer only in its portion in contact with the emitter. In the specific method disclosed in connection with FIG. 5B, an SiGe base layer 20 is epitaxied, then polysilicon layer 21 is grown. This application specifies at the beginning of paragraph [0058] that, between the depositions of the layers 20 and 21, a natural oxide film is formed on the surface of the SiGe layer 20.